The present invention relates to a measuring and testing apparatus for testing complex digital circuits; more particularly, to automatic digital in-circuit testers for testing digital circuits containing, but not limited to, large scale integrated circuits.
The in-circuit tester of the type disclosed herein is a tester that is capable of testing a circuit without regard to whether or not the electrical node into which a test signal is injected is connected to the output of another logic device. The disclosed in-circuit tester is capable of generating and applying a digital test signal to an output node of a logic device that is normally at a logic ground, and cause that output to go to a logic high without damaging the device. In other words, the use of the term "in-circuit" means that the device or circuit under test does not have to be isolated or removed from the surrounding circuits in order to apply test signals and to monitor its output.
Printed circuit boards containing complex digital integrated logic circuits interconnected by copper lands to form functional circuits, offer a greater challenge to prior-art in-circuit digital testers than they are able to meet. Prior art testers are able to select interconnection points between the digital components, referred to as the electrical nodes, and to apply test signals to a circuit or to monitor the response of the circuit to those signals. However, ever-increasing complex logic devices, such as micro-processors, are being developed and extensively used by today's circuit designers. Prior-art digital in-circuit testers are not capable of performing the numerous, rapid and varied tests required for such complex circuits.
One of the most significant developments in digital circuit technology in recent years has been the fabrication of large and complex digital circuits on a single chip of semiconductor material using large scale integration (LSI) techniques. These circuits typically contain a great number of transistors and other components which enable the designer to package a greater number of circuits in a relatively small volume. Research and development is underway in the form of very large scale integration (VLSI) for methods to manufacture an even greater number of circuits within a single chip. Where LSI has thousands of transistors per chip, VLSI has hundreds of thousands. As a result of the large number of circuits contained in LSI devices and the expected increases in circuit complexity from VLSI technology, the probability of chip failure has increased. Correspondingly, the importance of testing and diagnosis of chip failures has also increased. However, the prior-art digital in-circuit testers either are not capable of performing the complex tests required, or are too slow, due to the time required to generate all the necessary test signals to test these complex circuits.
Because of the increased packing density of digital circuits and the wide variety of logic functions available, LSI devices are enjoying widespread use in most digital circuits and systems which designers are presently producing. The reliability of such systems and circuits depend greatly on the reliability and accuracy of operation of the LSI devices and, thus, a need has arisen for new and sophisticated equipment and procedures for testing of these circuits. Such testing is relatively difficult because of the great number of different functional sections in each device. The problem is further compounded by the limited number of test nodes available to each integrated circuit for the connection of input and output signals.
Most of the functional sections of the integrated circuits consist of either combinational logic circuits or sequential logic circuits or some combination thereof. A combinational logic circuit is defined as one that consists entirely of gates (AND, OR, etc.). In a combinational logic system, no clock is required, and after the inputs have been established (disregarding settling time), the output is immediately available for checking to determine whether it conforms to the output signal that the circuit should correctly produce in response to the specified input signal. On the other hand, sequential circuits require a sequence of changes in the input test signals, such as a clock, before an output signal, produced in response to the test signals, can be examined to determine if the device correctly responded. Because of the complexity of the digital circuits and the fact that there exists only a limited access to the integrated circuit chip's circuits via the IC pins, many different test signals must be generated before all of the functional capabilities of the LSI device can be checked. In a great many instances, an output signal must be checked as to the pattern of one's and zero's that is produced in response to a known set of input test signals to determine if the chip is working properly.
It is thus apparent that an apparatus for testing circuit assemblies containing LSI circuits must be able to develop and analyze a large quantity of data and test signals. Further, the test apparatus must be adapted to perform tests on a large number of different LSI circuits having widely different transfer functions. To best accomplish this requirement, a computer controlled test system is preferred. The versatility of test programs both to generate the necessary test signals and to analyze the resulting response signals make the computer a necessary element of a test system for digital circuits having LSI devices. Although the computer offers great flexibility in selecting tests to be performed, often the response signal produced by the generated test signals consists of bit streams of data that would require excessive computer storage and execution time to analyze each and every bit so produced. Therefore, a technique of compressing the bit stream down into something that can readily be assimilated by the computer to obtain maximum usage of the computer's capabilities would be desirable. This compression of the long bit streams can be accomplished by using a cyclic redundancy check (CRC) coding technique, which logically combines each bit with those that went before, to generate a compact digital code or signature. This signature represents, almost uniquely, the length and pattern of one's and zero's that occured. The computer could then compare the measured code against a code for a correct response, to determine if the device is functioning properly.
A limitation of known computer-aided testers is the fact that the computer remains operatively tied into the test circuit during the performance of the test, because it is used as a source of test data. Because many LSI devices require lengthy and complex test signals in order to properly simmulate normal operations of the device, and because of speed limitations imposed by software-generated test signals, these types of computer-aided systems are capable of performing only a limited number of tests on these devices within a given time interval. However, if a computer-aided tester were provided which used intermediate test circuits to generate the test signals and to perform the functional tests, leaving for the computer only the initialization of the tester circuits prior to the test and the analysis of the results following the test, the power and flexibility of the computer could effectively be utilized.
Thus, it would be advantageous to provide a computer-controlled in-circuit digital tester for testing digital circuits employing the complex integrated circuits resulting from LSI technology in which appropriate test signals are generated and functional tests performed by intermediate test circuits, the results of which are analyzed by the computer.